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| GS1535A / GS9065A HD-LINX(R) II Multi-Rate SDI Automatic Reclocker GS1535A / GS9065A Data Sheet Features GS1535A * * * * * * * * * * * * * * * SMPTE 292M, 259M and 344M compliant Supports data rates of 143, 177, 270, 360, 540, 1483.5, 1485 Mb/s Supports DVB-ASI at 270Mb/s Pb-free and RoHS Compliant Footprint compatible with the GS1535, GS9065 and GS9065A Automatic Reclockers Auto and Manual Modes for rate selection Standards indication in Auto Mode 4:1 input multiplexer Lock Detect Output On-chip Input and Output Termination Differential 50 inputs and outputs Mute, Bypass and Autobypass functions SD/HD indication output to control GS1528A Dual Slew-Rate Cable Driver Single 3.3V power supply Operating temperature range: 0C to 70C Description The GS1535A/9065A is a Multi-Rate Serial Digital Reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. The GS1535A Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 292M, SMPTE 259M or SMPTE 344M compliant digital video signal. The GS9065A Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 259M or SMPTE 344M compliant digital video signal. The GS1535A/9065A removes the high frequency jitter components from the bit-serial stream. Input termination is on-chip for seamless matching to 50 transmission lines. An LVPECL compliant output interfaces seamlessly to the GS1528A/9068A Cable Driver. The GS1535A/9065A can operate in either auto or manual rate selection mode. In Auto mode the device will automatically detect and lock onto incoming SMPTE SDI data signals at any supported rate. For single rate data systems, the GS1535A/9065A can be configured to operate in Manual mode. In both modes, the device requires only one external crystal to set the VCO frequency when not locked and provides adjustment free operation. In systems which require passing of non-SMPTE data rates, the GS1535A/9065A can be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. The ASI/177 input pin allows for manual selection of support of either 177Mb/s or DVB-ASI inputs. The GS1535A/9065A is Pb-free, and the encapsulation compound does not contain halogenated flame retardant (RoHS Compliant). GS9065A * * * * * * * * * * * * * * SMPTE 259M and 344M compliant Supports data rates of 143, 177, 270, 360, and 540Mb/s Supports DVB-ASI at 270Mb/s Pb-free and RoHS Compliant Footprint compatible with the GS1535, GS9065 and GS1535A Automatic Reclockers Auto and Manual Modes for rate selection Standards indication in Auto Mode 4:1 input multiplexer Lock Detect Output On-chip Input and Output Termination Differential 50 inputs and outputs Mute, Bypass and Autobypass functions Single 3.3V power supply Operating temperature range: 0C to 70C Applications GS1535A * SMPTE 292M, SMPTE 259M and SMPTE 344M Serial Digital Interfaces GS9065A * SMPTE 259M and SMPTE 344M Serial Digital Interfaces. 31497 - 3 November 2005 1 of 27 www.gennum.com GS1535A / GS9065A Data Sheet XTAL+ XTAL- XTAL XTAL OUT+ OUT- LF+ LF- KBB XTAL OSC BUFFER RE-TIMER M U X DATA BUFFER DDO/DDO DDO_MUTE DDI 0 PHASE FREQUENCY DETECTOR D A T A M U X M U X CHARGE PUMP VCO DDI 1 PHASE DETECTOR DIVIDE BY 2,4,6,8,12,16 DIVIDE BY 152, 160, 208 DDI 2 DDI 3 DDI_SEL[1:0] CONTROL LOGIC BYPASS LOGIC SS[2:0] ASI/177 AUTO/MAN SD/HD LD AUTOBYPASS BYPASS GS1535A Functional Block Diagram XTAL+ XTAL- XTAL XTAL OUT+ OUT- LF+ LF- KBB XTAL OSC BUFFER RE-TIMER M U X DATA BUFFER DDO/DDO DDO_MUTE DDI 0 PHASE FREQUENCY DETECTOR D A T A M U X M U X CHARGE PUMP VCO DDI 1 PHASE DETECTOR DIVIDE BY 2,4,6,8,12 DIVIDE BY 152, 160 DDI 2 DDI 3 DDI_SEL[1:0] CONTROL LOGIC BYPASS LOGIC SS[2:0] ASI/177 AUTO/MAN SD LD AUTOBYPASS BYPASS GS9065A Functional Block Diagram 31497 - 3 November 2005 2 of 27 GS1535A / GS9065A Data Sheet Contents Features ........................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 1. Pin Out ......................................................................................................................4 1.1 GS1535A Pin Assignment ..............................................................................4 1.2 GS9065A Pin Assignment ..............................................................................5 1.3 GS1535A / GS9065A Pin Descriptions ...........................................................6 2. Electrical Characteristics ...........................................................................................9 2.1 Absolute Maximum Ratings ............................................................................9 2.2 DC Electrical Characteristics ..........................................................................9 2.3 AC Electrical Characteristics .........................................................................10 2.4 Solder Reflow Profiles ...................................................................................12 3. Input / Output Circuits .............................................................................................13 4. Detailed Description ................................................................................................17 4.1 Slew Rate Phase Lock Loop (S-PLL) ...........................................................17 4.2 VCO ..............................................................................................................18 4.3 Charge Pump ................................................................................................18 4.4 Frequency Acquisition Loop -- The Phase-Frequency Detector ..................19 4.5 Phase Acquisition Loop -- The Phase Detector ...........................................19 4.6 4:1 Input Mux ................................................................................................20 4.7 Automatic and Manual Data Rate Selection .................................................20 4.8 Bypass Mode ................................................................................................21 4.9 DVB-ASI Operation .......................................................................................21 4.10 Lock ............................................................................................................22 4.11 Output Drivers .............................................................................................22 4.12 Output Mute ................................................................................................22 5. Typical Application Circuits .....................................................................................23 6. Package & Ordering Information .............................................................................25 6.1 Package Dimensions ....................................................................................25 6.2 Packaging Data .............................................................................................26 6.3 Ordering Information .....................................................................................26 7. Revision History ......................................................................................................27 31497 - 3 November 2005 3 of 27 GS1535A / GS9065A Data Sheet 1. Pin Out 1.1 GS1535A Pin Assignment RSVD XTAL_OUT+ 50 XTAL_OUTVCC_CP VEE_CP XTAL+ XTALRSVD RSVD RSVD RSVD RSVD GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 49 VEE_DDO VCC_DDO DDO DDO_VTT DDO GND RSVD RSVD RSVD RSVD RSVD GND DDO_MUTE RSVD KBB SD/HD DDI0 DDI0_VTT DDI0 GND DDI1 DDI1_VTT DDI1 GND DDI2 DDI2_VTT DDI2 GND DDI3 DDI3_VTT DDI3 GND 1 2 3 4 5 6 7 8 9 10 11 12 P 13 14 15 16 GS1535A (TOP VIEW) GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 GND 17 DDI_SEL0 18 DDI_SEL1 19 BYPASS LF+ LF- 20 AUTOBYPASS 21 AUTO/MAN 22 VCC_VCO 23 VEE_VCO 24 SS0 25 SS1 26 SS2 27 ASI/177 28 LD 29 RSVD 30 VCC_DIG 31 VEE_DIG Figure 1-1: 64-Pin LQFP 31497 - 3 November 2005 4 of 27 GS1535A / GS9065A Data Sheet 1.2 GS9065A Pin Assignment RSVD XTAL_OUT+ 50 XTAL_OUTVCC_CP VEE_CP XTAL+ XTALRSVD RSVD RSVD RSVD RSVD GND 64 63 62 61 60 59 58 57 56 55 54 53 52 51 49 VEE_DDO VCC_DDO DDO DDO_VTT DDO GND RSVD RSVD RSVD RSVD RSVD GND DDO_MUTE RSVD KBB SD DDI0 DDI0_VTT DDI0 GND DDI1 DDI1_VTT DDI1 GND DDI2 DDI2_VTT DDI2 GND DDI3 DDI3_VTT DDI3 GND 1 2 3 4 5 6 7 8 9 10 11 12 P 13 14 15 16 GS9065A (TOP VIEW) GND 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 GND 17 DDI_SEL0 18 DDI_SEL1 19 BYPASS LF+ LF- 20 AUTOBYPASS 21 AUTO/MAN 22 VCC_VCO 23 VEE_VCO 24 SS0 25 SS1 26 SS2 27 ASI/177 28 LD 29 RSVD 30 VCC_DIG 31 VEE_DIG Figure 1-2: 64-Pin LQFP 31497 - 3 November 2005 5 of 27 GS1535A / GS9065A Data Sheet 1.3 GS1535A / GS9065A Pin Descriptions Table 1-1: GS1535A / GS9065A Pin Descriptions Pin Number 1, 3 2 4, 8, 12,16, 32, 37, 43, 49, 64 5, 7 6 9, 11 10 13, 15 14 17, 18 Name DDI0, DDI0 DDI0_VTT GND DDI1,DDI1 DDI1_VTT DDI2, DDI2 DDI2_VTT DDI3, DDI3 DDI3_VTT DDI_SEL[1:0] Type Input Passive Passive Input Passive Input Passive Input Passive Logic Input Description Serial digital differential input 0. Center tap of two 50 on-chip termination resistors between DDI0 and DDI0. Recommended connect to GND. Serial digital differential input 1. Center tap of two 50 on-chip termination resistors between DDI1 and DDI1. Serial digital differential input 2. Center tap of two 50 on-chip termination resistors between DDI2 and DDI2. Serial digital differential input 3. Center tap of two 50 on-chip termination resistors between DDI3 and DDI3. Serial digital input select. DDI_SEL1 0 0 1 1 DDI_SEL0 0 1 0 1 INPUT SELECTED DDI0 DDI1 DDI2 DDI3 19 BYPASS Logic Input Bypass the reclocker stage. When BYPASS is HIGH, it overwrites the AUTOBYPASS setting. 20 AUTOBYPASS Logic Input Automatically bypasses the reclocker stage when the PLL is not locked This pin is ignored when BYPASS is HIGH. 21 AUTO/MAN Logic Input Auto/Manual select. When set HIGH, the standard is automatically detected from the input data rate. When set LOW, the user must program the input standard using the SS[2:0] pins. 22 VCC_VCO Power Most positive power supply connection for the internal VCO section. Connect to 3.3V. 23 VEE_VCO Power Most negative power supply connection for the internal VCO section. Connect to GND. 31497 - 3 November 2005 6 of 27 GS1535A / GS9065A Data Sheet Table 1-1: GS1535A / GS9065A Pin Descriptions (Continued) Pin Number 24, 25, 26 Name SS[2:0] Type Bi-directional Description When AUTO/MAN is HIGH, SS[0:2] are outputs, displaying the data rate to which the PLL has locked. When AUTO/MAN is LOW, SS[0:2] are inputs, forcing the PLL to lock only to a selected data rate . SS2 SS1 SS0 DATA RATE SELECTED/FORCED (Mb/s) 143 177 270 360 540 1483.5/1485* 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 *Only applies to the GS1535A. For the GS9065A, when AUTO/MAN is LOW, the pin settings SS[0:2] = 101 will be ignored by the device. 27 ASI/177 Logic Input When set HIGH, the device disables the 177Mb/s data rate in the data rate detection circuit. This prevents a false lock to 177Mb/s when using DVB-ASI. When set LOW, 177Mb/s lock is possible, however, if a 270Mb/s ASI signal is applied, the device could false lock to the 177MHz signal. 28 LD Output Lock Detect. This pin is set HIGH by the device when the PLL is locked. 29 30 RSVD VCC_DIG Reserved Power Do not connect. Most positive power supply connection for the internal glue logic. Connect to 3.3V. 31 VEE_DIG Power Most negative power supply connection for the internal glue logic. Connect to GND. 33 SD/HD Output GS1535A: This signal will be set LOW by the device when the reclocker has locked to 1.485Gbps or 1.485/1.001Gbps, or when a non-SMPTE standard is applied (i.e. the device is not locked). It will be set HIGH when the reclocker has locked to 143Mbps, 177Mbps, 270Mbps, 360Mbps, or 540Mbps. GS9065A: This signal will go HIGH when the reclocker has locked to the input SD signal. It will be LOW otherwise. 34 KBB Analog Input Controls the loop bandwidth of the PLL. Leave this pin floating for serial reclocking applications. 35, 38 - 42 36 RSVD DDO_MUTE Reserved Logic Input Do not connect. Mutes the DDO/DDO outputs, when not in bypass mode. 31497 - 3 November 2005 7 of 27 GS1535A / GS9065A Data Sheet Table 1-1: GS1535A / GS9065A Pin Descriptions (Continued) Pin Number 43 44, 46 45 Name GND_DRV DDO, DDO DDO_VTT Type Passive Output Passive Description Recommended connect to GND. Differential Serial Digital Outputs. Do not connect. NOTE: This pin is not connected internally. Previous external application circuitry from the original GS1535/9065 may remain in order to maintain footprint compatibility. 47 VCC_DDO Power Most positive power supply connection for the DDO/DDO output driver. Connect to 3.3V. 48 VEE_DDO Power Most negative power supply connection for the DDO/DDO output driver. Connect to GND. 50, 51 52, 53 54 - 59 XTAL_OUT+, XTAL_OUTXTAL+, XTALRSVD Output Input Reserved Differential outputs of the reference oscillator used for monitoring or test purposes. Reference crystal input. Connect to the GO1535. Do Not Connect. NOTE: These pins are not connected internally. Previous external application circuitry from the original GS1535/9065 may remain in order to maintain footprint compatibility. 60 VEE_CP Power Most negative power supply connection for the internal charge pump. Connect to GND. 61 VCC_CP Power Most positive power supply connection for the internal charge pump. Connect to 3.3V. 62, 63 LF+, LF- Passive Loop filter capacitor connection. (CLF = 47nF). 31497 - 3 November 2005 8 of 27 GS1535A / GS9065A Data Sheet 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Supply Voltage Input ESD Voltage Storage Temperature Range Input Voltage Operating Temperature Range Value +3.6 VDC 2kV -50C < Ts < 125C Vcc + 0.5V 0C to 70C 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics VCC = 3.3V, TA = 0C to 70C, unless otherwise shown Parameter Supply Voltage Supply Current Power Consumption Logic Inputs DDI_SEL[1:0], BYPASS, AUTOBYPASS, AUTO/MAN, ASI/177, DDO_MUTE Logic Outputs SD/HD, LD, and LOS Bi-Directional Pins (Manual Mode) SS[2:0], AUTO/MAN = 0 Bi-Directional Pins (Auto Mode) SS[2:0], AUTO/MAN = 1 XTAL_OUT+, XTAL_OUT- Symbol VCC ICC - VIH VIL Conditions Operating Range TA=25C TA=25C High Low Min 3.1 - - 2.0 - Typ 3.3 195 645 - - Max 3.5 230 - - 0.8 Units V mA mW V V Test Levels 3 1 5 3 3 VOH VOL VIH VIL VOH VOL VOH VOL 250uA Load 250uA Load High Low High, 250uA Load Low, 250uA Load High Low Common Mode 2.4 - 2.0 - 2.4 - - - 1.65 + (VSID/2) - - - - - - VCC VCC - 0.285 - - 0.4 - 0.8 - 0.4 - - VCC -(VSID/2) V V V V V V V V V 3 3 3 3 1 1 7 7 1 Serial Input Voltage - 31497 - 3 November 2005 9 of 27 GS1535A / GS9065A Data Sheet Table 2-1: DC Electrical Characteristics (Continued) VCC = 3.3V, TA = 0C to 70C, unless otherwise shown Parameter Output Voltage, DDO/DDO TEST LEVELS Symbol - Conditions Common Mode Min - Typ VCC - (VOD/2) Max - Units V Test Levels 1 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2 or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics VCC = 3.3V, TA = 0C to 70C, unless otherwise shown Parameter Serial Input Data Rate Symbol - - Conditions GS1535A GS9065A Worst case modulation (e.g. square wave modulation) 143, 270, 360, 1485 Mb/s Min 143 143 0.8 Typ - - - Max 1485 540 - Units Mb/s Mb/s UI Test Levels 3 3 1 Serial Input Jitter Tolerance - PLL Lock Time Asynchronous GS1535A PLL Lock Time Synchronous t ALOCK t SLOCK t SLOCK - CLF=47nF, SD/HD=0 CLF=47nF, SD/HD=1 CLF=47nF 50 load (on chip) 50 load (on chip) 100 load (on chip) 100 load differential - - - - - - 100 1400 - - - - 114 106 - 1600 10 10 39 39 - - 800 2200 ms us us us ps ps mVp-p mVp-p 6,7 6,7 6,7 6,7 6,7 6,7 6,7 6,7 GS9065A PLL Lock Time Synchronous Serial Output Rise/Fall Time (20% - 80%) t SLOCK trDDO tfDDO Serial Input Swing Serial Output Swing VSID VOD 31497 - 3 November 2005 10 of 27 GS1535A / GS9065A Data Sheet Table 2-2: AC Electrical Characteristics (Continued) VCC = 3.3V, TA = 0C to 70C, unless otherwise shown Parameter Serial Output Jitter KBB = Float PRN, 223-1 Measurement is output jitter that includes input jitter from BERT. Symbol tOJ tOJ tOJ tOJ tOJ tOJ tOJ Conditions 143 Mb/s 177 Mb/s 270 Mb/s 360 Mb/s 540 Mb/s 1485 Mb/s (GS1535A only) Bypass 1.485 Gb/s, KBB = FLOAT (GS1535A only) Min - - - - - - - - Typ 0.02 0.02 0.02 0.03 0.03 0.06 0.06 1.75 Max - - 0.09 - 0.09 0.13 0.13 - Units UI UI UI UI UI UI UI MHz Test Levels 1 1 1 1 1 1 1 6,7 Loop Bandwidth BWLOOP BWLOOP 1.485 Gb/s, KBB = GND, <0.1dB Peaking (GS1535A only) - 3.2 - MHz 6,7 BWLOOP BWLOOP TEST LEVELS 270 Mb/s, KBB = FLOAT 270 Mb/s, KBB = GND - - 520 1000 - - KHz KHz 6,7 6,7 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2 or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test. 31497 - 3 November 2005 11 of 27 GS1535A / GS9065A Data Sheet 2.4 Solder Reflow Profiles The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 2-1. The recommended standard Pb reflow profile is shown in Figure 2-2. Temperature 60-150 sec. 20-40 sec. 260C 250C 3C/sec max 217C 6C/sec max 200C 150C 25C Time 60-180 sec. max 8 min. max Figure 2-1: Maximum Pb-free Solder Reflow Profile (Preferred) Temperature 60-150 sec. 10-20 sec. 230C 220C 3C/sec max 183C 6C/sec max 150C 100C 25C Time 120 sec. max 6 min. max Figure 2-2: Standard Pb Solder Reflow Profile (Pb-free package) 31497 - 3 November 2005 12 of 27 GS1535A / GS9065A Data Sheet 3. Input / Output Circuits VREF Figure 3-1: DDO_MUTE, BYPASS 8k VREF Figure 3-2: DDI_SEL[1:0], AUTOBYPASS, AUTO/MAN, ASI/177 LF+ LF- Figure 3-3: Loop Filter 31497 - 3 November 2005 13 of 27 GS1535A / GS9065A Data Sheet 250R 10p 250R 5K 5K XTAL+ XTAL- Figure 3-4: Crystal Input 1K 1K XTAL OUT+ XTAL OUT- Figure 3-5: Crystal Output Buffer 50 SDO 50 SDO Figure 3-6: Serial Data Outputs 31497 - 3 November 2005 14 of 27 GS1535A / GS9065A Data Sheet V REF KBB 500R Figure 3-7: KBB Figure 3-8: Indicator Outputs: SD/HD, LD 24k SS[2:0] vREF Figure 3-9: Standard Select/Indication Bi-directional Pins 31497 - 3 November 2005 15 of 27 GS1535A / GS9065A Data Sheet DDI[3:0] 50 1k 1k DDI_VTT 50 DDI[3:0] Figure 3-10: Serial Data Inputs 31497 - 3 November 2005 16 of 27 GS1535A / GS9065A Data Sheet 4. Detailed Description The GS1535A/9065A is a Multi-Rate Serial Digital Reclocker designed to automatically recover the embedded clock from a digital video signal and re-time the incoming video data. The GS1535A Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 292M, SMPTE 259M or SMPTE 344M compliant digital video signal. The GS9065A Serial Digital Reclocker will recover the embedded clock signal and re-time the data from a SMPTE 259M or SMPTE 344M compliant digital video signal. Using the functional block diagram (page 2) as a guide, Slew Rate Phase Lock Loop (S-PLL) on page 17 to Output Mute on page 22 describes each aspect of the GS1535A/9065A in detail. 4.1 Slew Rate Phase Lock Loop (S-PLL) The term "slew" refers to the output phase of the PLL in response to a step change at the input. Linear PLLs have an output phase response characterized by an exponential response whereas an S-PLL's output is a ramp response (see Figure 4-1). Because of this non-linear response characteristic, traditional small signal analysis is not possible with an S-PLL. 0.2 PHASE (UI) INPUT 0.1 OUTPUT 0.0 SLEW PLL RESPONSE 0.2 PHASE (UI) INPUT 0.1 OUTPUT 0.0 LINEAR (CONVENTIONAL) PLL RESPONSE Figure 4-1: PLL Characteristics 31497 - 3 November 2005 17 of 27 GS1535A / GS9065A Data Sheet The S-PLL offers several advantages over the linear PLL. The Loop Bandwidth of an S-PLL is independent of the transition density of the input data. Pseudo-random data has a transition density of 0.5 verses a pathological signal which has a transition density of 0.05. The loop bandwidth of a linear PLL will change proportionally with this change in transition density. With an S-PLL, the loop bandwidth is defined by the jitter at the data input. This translates to infinite loop bandwidth with a zero jitter input signal. This allows the loop to correct for small variations in the input jitter quickly, resulting in very low output jitter. The loop bandwidth of the GS1535A/9065A's PLL is defined at 0.2UI of input jitter. The PLL consists of two acquisition loops. First is the Frequency Acquisition (FA) loop. This loop is active when the device is not locked and is used to achieve lock to the supported data rates. Second is the phase acquisition (PA) loop. Once locked, the PA loop tracks the incoming data and makes phased corrections to produce a re-clocked output. 4.2 VCO The internal VCO of the GS1535A/9065A is a ring oscillator. It is trimmed at the time of manufacture to capture all data rates over temperature and operation voltage ranges. Integrated into the VCO is a series of programmable dividers used to achieve all serial data rates, as well as additional dividers for the frequency acquisition loop. 4.3 Charge Pump A common charge pump is used for the PLL of the GS1535A/9065A. During frequency acquisition, the charge pump has two states, "pump-up" and "pump-down," which is produced by a leading or lagging phase difference between the input and the VCO frequency. During phase acquisition, there are two levels of "pump-up" and two levels of "pump down" produced for leading and lagging phase difference between the input and VCO frequency. This is to allow for greater precision of VCO control. The charge pump produces these signals by holding the integrated frequency information on the external loop-filter capacitor, CLF. The instantaneous frequency information is the result of the current flowing through an internal resistor connected to the loop-filter capacitor. 31497 - 3 November 2005 18 of 27 GS1535A / GS9065A Data Sheet 4.4 Frequency Acquisition Loop -- The Phase-Frequency Detector An external crystal of 14.140 MHz is used as a reference to keep the VCO centered at the last known data rate. This allows the device to achieve a fast synchronous lock, especially in cases where a known data rate is interrupted. The crystal reference is also used to clock internal timers and counters. To keep the optimal performance of the reclocker over all operating conditions, the crystal frequency must be 14.140 MHz, +/-50ppm. The GO1535 meets this specification and is available from GENNUM. The VCO is divided by a selected ratio which is dependant on the input data rate. The resultant is then compared to the crystal frequency. If the divided VCO frequency and the crystal frequency are within 1% of each other, the PLL is considered to be locked to the input data rate. 4.5 Phase Acquisition Loop -- The Phase Detector The phase detector is a digital quadrature phase detector. It indicates whether the input data is leading or lagging with respect to a clock that is in phase with the VCO (I-clk) and a quadrature clock (Q-clk). When the phase acquisition loop (PA loop) is locked, the input data transition is aligned to the falling edge of I-clk and the output data is re-timed on the rising edge of I-clk. During high input jitter conditions (>0.25UI), Q-clk will sample a different value than I-clk. In this condition, two extra phase correction signals will be generated which instructs the charge pump to create larger frequency corrections for the VCO. i-PHASE ALIGNMENT EDGE DATA RE-TIMING EDGE I-clk q-clk q-PHASE ALIGNMENT EDGE INPUT DATA WITH JITTER 0.25UI 0.8UI RE-TIMED OUTPUT DATA Figure 4-2: Phase Detector Characteristics When the PA loop is active, the crystal frequency and the incoming data rate are compared. If the resultant is more that 2%, the PLL is considered to be unlocked and the system jumps to the FA loop. 31497 - 3 November 2005 19 of 27 GS1535A / GS9065A Data Sheet 4.6 4:1 Input Mux The 4:1 input mux allows the connection of four independent streams of video/data. There are four differential inputs (DDI[3:0] and DDI[3:0]). The active channel can be selected via the DDI_SEL[1:0] pins. Table 4-1 shows the input selected for a given state at DDI_SEL[1:0]. Table 4-1: Bit Pattern for Input Select DDI_SEL[1:0] 00 01 10 11 Selected Input DDI0 DDI1 DDI2 DDI3 The DDI inputs are designed to be DC interfaced with the output of the GS1524A/9064A Cable Equalizer. There are on chip 50 termination resistors which come to a common point at the DDI_VT pins. Connect a 10nF capacitor to this pin and connect the other end of the capacitor to ground. This terminates the transmission line at the inputs for optimum performance. If only one input pair is used, connect the unused positive inputs to +3.3V and leave the unused negative inputs floating. This helps to eliminate crosstalk from potential noise that would couple to the unused input pair. 4.7 Automatic and Manual Data Rate Selection The GS1535A/9065A can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. The AUTO/MAN pin selects automatic data rate detection mode (Auto mode) when HIGH and manual data rate selection mode (Manual mode) when LOW. In Auto mode, the SS[2:0] bi-directional pins become outputs and the bit pattern indicates the data rate that the PLL is locked to (or previously locked to). The "search algorithm" cycles through the data rates and starts over if that data rate is not found (see Figure 4-3). POWER-UP 143 Mb\s 177 Mb\s 270Mb\s 360 Mb\s 1.485Mb\s (GS1535A only) 540 Mb\s Figure 4-3: Data Rate Search Pattern 31497 - 3 November 2005 20 of 27 GS1535A / GS9065A Data Sheet In Manual mode, the SS[2:0] pins become inputs and the data rate can be programmed by the application layer. In this mode, the search algorithm is disabled and the PLL will only lock to the data rate selected. Table 4-2 shows the SS[2:0] pin settings for either the data rate selected (in Manual mode) or the data rate that the PLL has locked to (in Auto mode). Table 4-2: Data Rate Indication/Selection Bit Pattern SS[2:0] 000 001 010 011 100 101* Data Rate (Mb/s) 143 177 270 360 540 1485/1483.5 * This setting only applies to the GS1535A. For the GS9065A, when AUTO/MAN is LOW, the pin settings SS[0:2] = 101 will be ignored by the device. 4.8 Bypass Mode In Bypass mode, the GS1535A/9065A passes the data at the inputs directly to the outputs. There are two pins that control the bypass function: BYPASS and AUTOBYPASS. When BYPASS is set HIGH by the application layer, the GS1535A/9065A will be in Bypass mode. When AUTOBYPASS is set HIGH by the application layer, the GS1535A/9065A will be configured to enter Bypass mode only when the PLL has not locked to a data rate. When BYPASS is set HIGH, AUTOBYPASS will be ignored. When the PLL is not locked, and both BYPASS and AUTOBYPASS are set LOW, the serial digital output DDO/DDO will produce invalid data. 4.9 DVB-ASI Operation The GS1535A/9065A will also re-clock DVB-ASI at 270 Mb/s. When reclocking DVB-ASI data set the ASI/177 pin HIGH to prevent a false lock to 177Mb/s. If ASI/177 is not set HIGH, a false lock may occur since there is a harmonic present in idle patterns (K28.5) which is very close the 177 Mb/s data rate (EIC 1179). Note that setting the ASI/177 pin HIGH will disable the 177 Mb/s search when the device is in Auto mode, consequently the GS1535A/9065A will not lock to that data rate. 31497 - 3 November 2005 21 of 27 GS1535A / GS9065A Data Sheet 4.10 Lock The LOCK DETECT signal, LD, is an active high output which indicates when the PLL is locked. The internal lock logic of the GS1535A/9065A includes a system which monitors the Frequency Acquisition Loop and the Phase Acquisition Loop as well as a monitor to detect harmonic lock. 4.11 Output Drivers The device's serial digital data outputs (DDO/DDO) have a nominal voltage of 800mv single ended or 1600mV differential when terminated into a 50 load. 4.12 Output Mute The DDO_MUTE pin is provided to allow muting of the re-timed output. When the PLL is locked and the device is reclocking, setting DDO_MUTE = LOW will force the serial digital outputs DDO/DDO to mute. However, if the GS1535A/9065A is in Bypass mode, (AUTOBYPASS = HIGH and/or BYPASS = HIGH), DDO_MUTE will have no effect on the output. 31497 - 3 November 2005 22 of 27 GS1535A / GS9065A Data Sheet 5. Typical Application Circuits No te : P in s 4 5 , 5 4 , 5 5 , a n d 57 are not connected i nternal l y. A ny previ ous ci rcui try from th e o r ig in a l GS 1 5 3 5 m a y remai n connected i n order to mai ntai n footpri nt compati bi l i ty. GO1535 (14.140MH z) 47n 3 .3 V 100 10n 55 GND 64 63 62 61 60 59 58 57 56 54 53 X TAL+ 5 2 51 X TAL_ OU T50 X TAL_ OU T+ VCC_CP X TAL- VEE_CP GN D NC LF+ NC NC LF- NC NC NC 49 1 DDI0 DDI0 _V T DDI0 GND DDI1 DDI1 _V T DDI1 GND DDI2 DDI2 _V T DDI2 GND DDI3 DDI3 _V T DDI3 A U TOB YPA SS A U TO/MA N GND D D I_SEL0 D D I_SEL1 B YPA SS VC C _VC O VEE_D D O VC C _D D O DDO D D O_VTT DDO GND R SVD 48 10n 47 46 45 44 43 42 41 3.3V D ATA INPUT 0 Z o = 50 2 10n 3 4 5 Zo = 50 DATA OUTPUT D AT A INPUT 1 Z o = 50 6 10n 7 8 9 GS 1 5 3 5 A R SVD 40 R SVD R SVD R SVD GND D D O_MU TE R SVD KBB SD/HD VC C _D IG 33 S D /H D 39 38 37 36 35 34 S D O_ M U TE D A TA INPUT 2 Z o = 50 10 10n 11 12 13 D A TA INPUT 3 Z o = 50 14 10n 15 16 VEE_VC 0 VEE_D IG 31 3.3V A SI/177 R SVD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 10n DDI_S E L 0 DDI_S E L 1 AS I_1 7 7 3.3V 10n 32 GND SS0 SS1 SS2 LD LD Note: All resistors in ohms and all capacitors in Farads. Figure 5-1: GS1535A Typical Application Circuit 31497 - 3 November 2005 23 of 27 GS1535A / GS9065A Data Sheet Note: Pins 45, 54, 55, and 5 7 a r e n o t c o n n e c t e d in t e r n a lly. A n y p r e vio u s c ir c u it r y f r o m the original GS9065 may r e ma in c o n n e c t e d in o r d e r t o ma in t a in f o o t p r in t c o mp a t ib ilit y. GO1 5 3 5 ( 1 4 . 1 4 0 MH z) 47n 3.3V 100 10n 55 G ND 64 63 62 61 60 59 58 57 56 54 53 X TA L+ 52 51 X TA L_ O UT50 X TA L_ O UT+ V CC_ CP X TA L- V E E _ CP G ND NC LF+ NC NC LF- NC NC NC 49 1 DDI0 DDI0_ VT DDI0 GND DDI1 DDI1_ VT DDI1 GND DDI2 DDI2_ VT DDI2 GND DDI3 DDI3_ VT DDI3 A U T OB Y P A S S A U T O/ MA N GND D D I _S E L 0 D D I _S E L 1 BYPASS V C C _V C O V E E _D D O V C C _D D O DDO D D O_V T T DDO GN D RSVD 48 1 0n 47 46 45 44 43 42 41 3.3V DAT A IN PU T 0 Zo = 50 2 10n 3 4 5 Zo = 50 DATA OUTPUT DA T A IN PU T 1 Zo = 50 6 10n 7 8 9 GS9065A RSVD 40 RSVD RSVD RSVD GN D D D O_MU T E RSVD KBB SD V C C _D I G 33 SD 39 38 37 36 35 34 SDO _ MUTE DAT A IN PU T 2 Z o = 50 10 10n 11 12 13 DAT A IN PU T 3 Zo = 50 14 10n 15 16 V E E _V C 0 V E E _D I G 31 3.3V ASI/177 RSVD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 10n DDI_ SEL0 DDI_ SEL1 ASI_ 177 3.3V 10n 32 GN D SS0 SS1 SS2 LD LD Note: All resistors in ohms and all capacitors in Farads. Figure 5-2: GS9065A Typical Application Circuit 31497 - 3 November 2005 24 of 27 GS1535A / GS9065A Data Sheet 6. Package & Ordering Information 6.1 Package Dimensions Table X 0 0 0 0 NOTE: Diagram shown is representative only. Table X is fixed for all pin sizes, and Table Y is specific to the 64-pin package. Table Y SYMBOL MILLIMETER MIN b e D2 E2 0.17 NOM 0.20 MAX 0.27 MIN 64L I NCH NO M MAX 0. 007 0. 008 0. 011 0. 020 B S C 0. 295 0. 295 0.50 BSC 7.50 7.50 TOLERANCES OF FORM AND POSITION aaa bbb ccc 0.20 0.20 0.08 0. 008 0. 008 0. 003 31497 - 3 November 2005 25 of 27 GS1535A / GS9065A Data Sheet 6.2 Packaging Data Parameter Package Type Package Drawing Reference Moisture Saturation Level Junction to Case Thermal Resistance, j-c Junction to Air Thermal Resistance, j-a (at zero airflow) Psi Pb-free and RoHS Compliant Value 10mm x 10mm 64-pin LQFP ASE 64-06-280-1384 3 18.1C/W 47.8C/W 1.1C/W Yes 6.3 Ordering Information Part Number GS1535A GS9065A GS1535ACFUE3 GS9065ACFUE3 Package Pb-free 64-pin LQFP Pb-free 64-pin LQFP Temperature Range 0C to 70C 0C to 70C 31497 - 3 November 2005 26 of 27 GS1535A / GS9065A Data Sheet 7. Revision History Version A 0 ECR 133493 134398 PCN - - Date April 2004 September 2004 Changes and/or Modifications New Document. Convert to Preliminary Data Sheet. Updated pin descriptions. Updated Electrical Characteristics. Added Packaging Data section detailing package information. Corrected minor typing errors in pin description table and typical application circuits. Corrected block diagrams and pin description table to reflect mute functionality of the device. Removed all references to the Serial Clock Output. Updated all `Green' references to `RoHS Compliant'. Updated TTL input circuit and Standard Selection/Indication circuit diagrams. Corrected minor typing errors in electrical characteristics tables. Converted to Data Sheet. Revised maximum output swing to 2200 mV in AC Electrical Characteristics on page 10. 1 135364 - February 2005 2 136782 - May 2005 3 138505 37280 November 2005 CAUTION ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION DATA SHEET The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible. GENNUM CORPORATION Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 GENNUM JAPAN CORPORATION Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505 GENNUM UK LIMITED 25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. (c) Copyright 2004 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com 31497 - 3 November 2005 27 27 of 27 |
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